A multi-service telecommunications system may provide customer services utilizing both synchronous serial bit streams and channelized Time Division Multiplexed (TDM) bit streams. A synchronous serial bit stream such as that utilizing the V.35 protocol transports bit oriented data. A channelized TDM bit stream such as a T1 or E1 bit stream may transport byte or bit oriented data in 125 microsecond (us) frames, using bandwidth allocations of 56 thousand (k) or 64k Bits Per Second (bps) “DS0s”. The 56k and 64k bandwidth allocations depend on whether the Least Significant Bit (LSB) of the 8-bit DS0 time slot is preserved end-to-end. Selected DS0s may or may not be contiguous within the TDM frame.
The TDM data stream and synchronous serial data interfaces each transport clock information between endpoints. A synchronous serial interface includes separate and distinct clock connections used for synchronizing transmit and receive data. Clocking for the channelized TDM streams is embedded within the data stream and extracted on either receiving end using known recovery schemes.
Some TDM data streams, such as those provided by T1 services, provide 1<=N<=24 DS0 time slots for each frame. Other TDM data streams, such as those provided by E1 services, provide 1<=N<=32 DS0s for each frame. If the synchronous serial data rate is equal to the bandwidth used by a multiple (N) number of DS0s, bi-directional data can be cross connected between the serial data stream and the selected N DS0s within the TDM stream using First In-First Out (FIFO) buffers. Rate adaptation FIFOs are normally sized for the maximum memory depth necessary for buffering data bursts occurring within the frame period. For example, the minimum required FIFO depth, in bits is N=(32 DS0s/frame)*(8 bits/DS0)*2. Reading out from the FIFO is enabled when the incoming data to the FIFO has reached half this depth.
In these FIFO designs, when the number of time slots used per frame (N) is small, more incoming frames are required before the FIFO will reach the “fill” level required to enable data to be read out from the FIFO. This increases data latency. Many FIFOs only include a single “half full” indicator that does not permit much visibility into the actual FIFO fill level.
The present invention addresses this and other problems associated with the prior art.